搜索资源列表
sl361_schematic-gerber
- fpga-sdram开发板-sch,本原理图是xilinx公司s3系列开发板的sdram-- SDRAM development board - sch, the diagram is Xilinx companies s3 series of development board SDRAM
11lab01
- 一组开发基于XILINX FPGA开发DSP算法的应用资料，具有实用性，可操作性。（1）-a group Xilinx FPGA-based DSP algorithm development of the information is useful, operability. (1)
12lab02
- 一组开发基于XILINX FPGA开发DSP算法的应用资料，具有实用性，可操作性。（2）-a group Xilinx FPGA-based DSP algorithm development of the information is useful, operability. (2)
13lab03
- 一组开发基于XILINX FPGA开发DSP算法的应用资料，具有实用性，可操作性。（3）-a group Xilinx FPGA-based DSP algorithm development of the information is useful, operability. (3)
14lab04
- 一组开发基于XILINX FPGA开发DSP算法的应用资料，具有实用性，可操作性。（4）-a group Xilinx FPGA-based DSP algorithm development of the information is useful, operability. (4)
15lab05
- 一组开发基于XILINX FPGA开发DSP算法的应用资料，具有实用性，可操作性。（5）-a group Xilinx FPGA-based DSP algorithm development of the information is useful, operability. (5)
XilinxFree.lic
- 这是许可在Xilinx Vivado 2015利用免费的IP核生成(This is the license to utilize free IP core generation in Xilinx Vivado 2015)
FSK
- 首先利用IP核记录sin和con波形，然后进行FSK调制，信息为数字信息(Firstly, the IP kernel is used to record the sin and con waveforms, and then the FSK is modulated, and the information is digital information)
MAKEAMIF
- 用于生成xilinx开发环境中存储器ip core的mif数据文件的程序代码。(this program is used to generate mif file used by xilinx memory ip core.)
MAKEXCOE
- 用于生成xilinx开发环境中存储器ip core的coe数据文件的程序代码。(this program is used to generate coe file used by xilinx memory ip core.)
Half-Adder
- This is an example to implement an Half-adder for xilinx FPGA
Xilinx 6 Family2
- and blogs ask visitors to register before they can view content, post comments or download something. Temp-Mail - is most advanced throwaway email service that helps you avoid spam and stay safe.
Xilinx 6 Family4
- a service that allows to receive email at a temporary address that self-destructed after a certain time elapses. It is also known by names like : tempmail, 10minutemail, throwaway email, fake-mail or trash-mail. Many forums
Xilinx 6 Family55
- a service that allows to receive email at a temporary address that self-destructed after a certain time elapses. It is also known by names like : tempmail, 10minutemail, throwaway email, fake-mail or trash-mail. Many forums a service that allows to r
Xilinx 6 Family666
- a service that allows to receive email at a temporary address that self-destructed after a certain time elapses. It is also known by names like : tempmail, 10minutemail, throwaway email, fake-mail or trash-mail. Many forums
Adept SDKv1-3
- 开发板资料，适用于赛灵思的板子，欢迎大家下载(Examine your code to determine if this port should be declared as an INOUT, or if the assignment to this port should not have been made. If this signal connects to submodules, consider the type and lower-level functionality of
BMD_design_gen2_x4_Chipscope
- 此文件是Xilinx公司的PCIE演示文档，可验证实现PCIE的基本功能(This file is Xilinx's PCIE demonstration document that validates the basic functions of the implementation of PCIE)
try
- 利用xilinx公司开发的vivado平台中的IP核-加法器，实现加法(The addition of IP core adder to the vivado platform developed by Xilinx is applied.)
xapp794
- 里面分为八个实验，一步一步教你使用system genertor for dsp 生成能供vivado使用的IP核文件。(It is divided into eight experiments, which teach you to use system genertor for DSP step by step to generate IP core files that can be used for vivado.)
好-无线通信FPGA设计-Xilinx
- 《无线通信FPGA设计》以Xilinx公司的FPGA开发平台为基础，综合FPGA和无线通信技术两个方向，通过大量的FPGA开发实例，较为详尽地描述了无线通信中常用模块的原理和实现流程，包括数字信号处理基础、数字滤波器、多速率信号处理、数字调制与解调、信道编码、系统同步、自适应滤波算法、最佳接收机，以及WCDMA系统的关键技术。《无线通信FPGA设计》概念明确、思路清晰，追求全面、系统、实用，使读者能够在较短的时间内具备无线通信领域的FPGA开发能力。(The design of wireless